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74LS109 - Dual J-K Positive-edge-triggered Flip-Flops

74LS109 - Dual J-K Positive-edge-triggered Flip-Flops

74LS109 - Dual J-K Positive-edge-triggered Flip-Flops

This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the J and K inputs may be changed while the clock is HIGH or LOW as long as setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.

Features:

  • Two Independent JK Positive Edge Triggered Flip-Flops
  • Separate Preset and Clear Inputs
  • Fast Switching Times
  • Operating Temperature up to 70oC
  • Standard TTL Switching Voltages


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  • Views: 1199
  • Product Code: 74LS109 - Dual J-K Positive-edge-triggered Flip-Flops
  • Availability: In Stock
  • Rs12.50

Tags: 74ls109 - dual j-k positive-edge-triggered flip-flops, flip, flop, ic, semiconductor, 74ls109, 74ls, ls109, dual, jk, positive, trigger

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